资料下载
飞思卡尔SSI模块培训资料
tutu27
分享资料个
Independent or shared transmit and receive sections with separate
or shared internal/external clocks and frame syncs, operating in
master or slave mode
Normal mode with frame sync
Network mode allowing multiple devices to share the port with as
many as 32 time slots
Gated clock mode with no frame sync
TM Freescale Semiconductor Confidential and Proprietary Information. Freescale. and the Freescale logo are trademarks
of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. . Freescale Semiconductor, Inc. 2006.
2 sets of transmit and receive FIFOs, each is 15x32bits
Programmable data interface mode: I2S, lsb or msb-aligned
Programmable word length (8,10,12,16,18,20,22 or 24bits)
AC97 support
Transmit and receive time slot mask registers for reduced CPU
overhead
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
