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Using the Timer Interrupt Syst
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2009-04-01
fansz
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Interrupts are used to respond to asynchronous requests from a certain part of the
microcontroller that needs to be serviced. Each peripheral in the TriCore as well as the
Bus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPU
itself can generate an interrupt request.
This document will show how to set up the TriCore registers to perform an interrupt service
request triggered by a 32-bit timer overflow.
The general-purpose timer unit, GPTUx, consists of three basic 32-bit timers, (T0, T1, and
T2). The three timers can solve many application tasks, such as timing events and
recording events. T0 and T1 are identical, while T2 offers a different functionality. The
three timers are able to operate independently from each other. The GPTUx can generate
eight different service requests. This document will focus on T0 as the timer in the
example, and it will utilize GTSRC0 as the selected service request node with SR00 as the
selected service request source.
Timer T0 consists of four eight-bit blocks (indexed from ‘A‘ to ‘D‘), including the actual
timer count register and the associated reload register. These blocks can either run
independently as eight-bit timers or can be concatenated to form wider timers (16, 24 , or
32 bits).
Note: Please refer to the User’s Manual for additional information on the GPTUx and the
Interrupt System of the TriCore.
microcontroller that needs to be serviced. Each peripheral in the TriCore as well as the
Bus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPU
itself can generate an interrupt request.
This document will show how to set up the TriCore registers to perform an interrupt service
request triggered by a 32-bit timer overflow.
The general-purpose timer unit, GPTUx, consists of three basic 32-bit timers, (T0, T1, and
T2). The three timers can solve many application tasks, such as timing events and
recording events. T0 and T1 are identical, while T2 offers a different functionality. The
three timers are able to operate independently from each other. The GPTUx can generate
eight different service requests. This document will focus on T0 as the timer in the
example, and it will utilize GTSRC0 as the selected service request node with SR00 as the
selected service request source.
Timer T0 consists of four eight-bit blocks (indexed from ‘A‘ to ‘D‘), including the actual
timer count register and the associated reload register. These blocks can either run
independently as eight-bit timers or can be concatenated to form wider timers (16, 24 , or
32 bits).
Note: Please refer to the User’s Manual for additional information on the GPTUx and the
Interrupt System of the TriCore.
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