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CD4015.pdf
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2008-04-02
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The CD4015BC contains two identical, 4-stage, serialinput/
parallel-output registers with independent “Data”,
“Clock,” and “Reset” inputs. The logic level present at the
input of each stage is transferred to the output of that stage
at each positive-going clock transition. A logic high on the
“Reset” input resets all four stages covered by that input.
All inputs are protected from static discharge by a series
resistor and diode clamps to VDD and VSS.
Features
Wide supply voltage range: 3.0V to 18V
High noise immunity: 0.45 VDD (typ.)
Low power TTL: Fan out of 2 driving 74L
compatibility: or 1 driving 74LS
Medium speed operation: 8 MHz (typ.) clock rate
Fully static design: @VDD − VSS = 10V
Applications
• Serial-input/parallel-output data queueing
• Serial to parallel data conversion
• General purpose register
parallel-output registers with independent “Data”,
“Clock,” and “Reset” inputs. The logic level present at the
input of each stage is transferred to the output of that stage
at each positive-going clock transition. A logic high on the
“Reset” input resets all four stages covered by that input.
All inputs are protected from static discharge by a series
resistor and diode clamps to VDD and VSS.
Features
Wide supply voltage range: 3.0V to 18V
High noise immunity: 0.45 VDD (typ.)
Low power TTL: Fan out of 2 driving 74L
compatibility: or 1 driving 74LS
Medium speed operation: 8 MHz (typ.) clock rate
Fully static design: @VDD − VSS = 10V
Applications
• Serial-input/parallel-output data queueing
• Serial to parallel data conversion
• General purpose register
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dz_ycy
2015-04-17
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