资料下载
×
基于FPGA的Kohonen竞争网络硬件实现
消耗积分:3 |
格式:rar |
大小:151 |
2009-06-18
479809
分享资料个
本文介绍了神经网络VLSI硬件实现的基本情况和VerilgHDL硬件设计方法的概念，在此基础上利用FPGA设计出了Kohonen竞争网络硬件电路，其工作频率为33Mhz，并对其工作过程进行了较详细的分析，给出了综合仿真的测试结果。
关键词：神经网络硬件实现 Kohonen竞争网络算法 VerilgHDL FPGA
Abstract: This paper introduces the basic complexion of neural network VLSI hardware realization and the concept of VerilgHDL hardware’s design. Based on that, it designs Kohonen competitive network hardware circuit by utilizing FPGA, which working frequency is 33Mhz. Then in this paper detailedly analyses its working process, and provides the testing result of integrated simulation.
Keywords: neural network hardware realization; Kohonen competitive network arithmetic; VerilgHDL; FPGA
关键词：神经网络硬件实现 Kohonen竞争网络算法 VerilgHDL FPGA
Abstract: This paper introduces the basic complexion of neural network VLSI hardware realization and the concept of VerilgHDL hardware’s design. Based on that, it designs Kohonen competitive network hardware circuit by utilizing FPGA, which working frequency is 33Mhz. Then in this paper detailedly analyses its working process, and provides the testing result of integrated simulation.
Keywords: neural network hardware realization; Kohonen competitive network arithmetic; VerilgHDL; FPGA
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
