资料下载
×
以AT89C51为例,介绍带闪速存储器的微控制器的结构
消耗积分:5 |
格式:rar |
大小:237 |
2009-06-27
分享资料个
• 8-Bit CPU Optimized for Control Applications
• Extensive Boolean Processing Capabilities (Single-Bit Logic)
• On-Chip Flash Program Memory
• On-Chip Data RAM
• Bidirectional and Individually Addressable I/O Lines
• Multiple 16-Bit Timer/Counters
• Full Duplex UART
• Multiple Source/Vector/Priority Interrupt Structure
• On-Chip Clock Oscillator
• On-chip EEPROM (AT89S series)
• SPI Serial Bus Interface (AT89S Series)
• Watchdog Timer (AT89S Series)
The basic architectural structure of the AT89C51 core is shown in Figure 1.
• Extensive Boolean Processing Capabilities (Single-Bit Logic)
• On-Chip Flash Program Memory
• On-Chip Data RAM
• Bidirectional and Individually Addressable I/O Lines
• Multiple 16-Bit Timer/Counters
• Full Duplex UART
• Multiple Source/Vector/Priority Interrupt Structure
• On-Chip Clock Oscillator
• On-chip EEPROM (AT89S series)
• SPI Serial Bus Interface (AT89S Series)
• Watchdog Timer (AT89S Series)
The basic architectural structure of the AT89C51 core is shown in Figure 1.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
