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Interconnection Noise in VLSI
张磊
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Interconnections are a most important design issue nowadays. Trends in the
microelectronic industry are leading to unwanted interconnect effects, especially
noise, becoming more important. This increasing importance is mainly
due to three reasons: increasing integration, increasing signal frequency spectrum
components, and increasing complexity.
The increase in integration and frequency of signals account for coupling
problems between adjacent lines and a growing importance of parasitic components
(capacitance and inductance). These two phenomena introduce analog
effects in digital design, and are therefore direct causes of the noise problem.
The increase in complexity is perhaps more indirectly related to noise and
the interconnection problem, but it is also very important. The drive to reduce
the time to market of new electronic products make design verification extremely
important and this pre-fabrication verification must be as accurate as
possible to reduce the risk of having to redesign failed prototypes. However,
the analog effects introduced by interconnections make traditional digital verification
tools inappropriate for addressing the problem. Recently there have
been many advances in interconnect simulation algorithms and efficient simulators
can calculate solutions for sophisticated models. This is a very important
subject and, with these algorithms and computer availability, accurate noise
waveforms for a small number of coupled interconnections can nowadays be
calculated easily. The problem is that from the point of view of the whole integrated
system, the applicability of these sophisticated models is necessarily
limited because today’s digital designs are so complex and the number of interconnections
is so large that a complete electrical simulation of the whole chip
is impossible, as it would take weeks or months.
Given this complexity problem for verification, there are two possible solutions:
one is to simplify the interconnect models. The other is to address
interconnect issues from the beginning of the design process, so they can be in
some way implemented as design rules in the design flow.
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