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Unique Chips and Systems
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Growing on-chip wire delays, coupled with complexity and power limitations,
have placed severe constraints on the issue-width scaling of centralized
superscalar architectures. As a result, recent microprocessor designs
have backed away from powerful uniprocessors, instead favoring multiple
simpler cores on a single die. Partitioning the chip into a collection of processors communicating via a common memory system mitigates some of the
technology scaling challenges, but increases the burden on software to providemultiple threads to execute concurrently across the cores.
An alternative is to pursue more powerful uniprocessors, but design them
so that they are scalable and tolerant of technology and complexity scaling.
Ideally, such wide-issue processors would be tiled [30], meaning composed
of multiple replicated, communicating design blocks. Because of multicycle
communication delays across these large processors, control must be distributed
across the tiles. We advocate the use of microarchitectural networks
(or micronets) for routing control and data among the tiles. Micronets provide
high-bandwidth, flow-controlled transport for control or data in a wiredominated
processor by connecting the multiple tiles, each of which is a client on one or more micronets. Higher-level microarchitectural protocols direct global control across themicronets and tiles in a manner invisible to software.
In this chapter,we describe the architecture and implementation of the Teraop,
Reliable, Intelligently-adaptive Processing System (TRIPS) processor—a
distributed, tiled microarchitecture. In particular, we discuss TRIPS tile partitioning,micronet connectivity, anddistributedprotocols thatprovide global
services in the TRIPS processor, including distributed fetch, execution, flush,
and commit. Although some of our prior publications have described the
TRIPS approach to exploiting parallelism as well as high-level performance
results [20,3], this chapter examines in detail the intertile connectivity and
protocols that have resulted from reducing the high-level design to silicon.
The key concepts that differentiate TRIPS from other tiled architectures such
as RAW[30] are the dynamic scheduling and execution which require distributed
dynamic hardware protocols to provide the means to extract both
irregular and regular concurrency.
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