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基于FPGA的RTL级USB2.0协议层设计与实现
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2009-12-14
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文中重点阐述了用VerilogHDL 语言对USB2.0 协议层关键模块的RTL 级设计和验证
工作，并在XILINX ISE 软件平台上进行了FPGA 综合。通过在ModelSim6.1 上仿真和ISE7.1上综合结果表明本文设计的USB 协议层模块是正确的。
关键词：FPGA，通用串行总线，VerilogHDL，协议层，RTL
Design and verification of USB protocol layer based on FPGA
YIN Baqun ZHOU Xianzhong
（Department of Control and Systems Engineering, Nanjing University, Nanjing, 210093）
Abstract As the main part of the paper, the design and verification of USB protocol layer key
modules are described in detail. Modules of USB2.0 protocol layer controller are designed in RTL by using VerilogHDL, and synthesized on the ISE platform of XILINX. The validity of the
modules of USB protocol layer is approved by simulation and synthesis.
Keyword FPGA, Universal Serial Bus, VerilogHDL, Protocol Layer, RTL
工作，并在XILINX ISE 软件平台上进行了FPGA 综合。通过在ModelSim6.1 上仿真和ISE7.1上综合结果表明本文设计的USB 协议层模块是正确的。
关键词：FPGA，通用串行总线，VerilogHDL，协议层，RTL
Design and verification of USB protocol layer based on FPGA
YIN Baqun ZHOU Xianzhong
（Department of Control and Systems Engineering, Nanjing University, Nanjing, 210093）
Abstract As the main part of the paper, the design and verification of USB protocol layer key
modules are described in detail. Modules of USB2.0 protocol layer controller are designed in RTL by using VerilogHDL, and synthesized on the ISE platform of XILINX. The validity of the
modules of USB protocol layer is approved by simulation and synthesis.
Keyword FPGA, Universal Serial Bus, VerilogHDL, Protocol Layer, RTL
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