×

74HC138 datasheet

消耗积分:10 | 格式:rar | 大小:133 | 2008-08-06

哈哈哈

分享资料个

MM54HC138/MM74HC138
3-to-8 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technology,
and is well suited to memory address decoding or data
routing applications. The circuit features high noise immunity
and low power consumption usually associated with
CMOS circuitry, yet has speeds comparable to low power
Schottky TTL logic.
The MM54HC138/MM74HC138 has 3 binary select inputs
(A, B, and C). If the device is enabled these inputs determine
which one of the eight normally high outputs will go
low. Two active low and one active high enables (G1, G2A
and G2B) are provided to ease the cascading of decoders.
The decoder's outputs can drive 10 low power Schottky TTL
equivalent loads, and are functionally and pin equivalent to
the 54LS138/74LS138. All inputs are protected from damage
due to static discharge by diodes to VCC and ground.
Features
Y Typical propagation delay: 20 ns
Y Wide power supply range: 2V±6V
Y Low quiescent current: 80 mA maximum (74HC Series)
Y Low input current: 1 mA maximum
Y Fanout of 10 LS-TTL loads

声明:本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人,不代表电子发烧友网立场。文章及其配图仅供工程师学习之用,如有内容侵权或者其他违规问题,请联系本站处理。 举报投诉

评论(1)
发评论
jx1016038368 2014-12-10
0 回复 举报
很好,资料很全! 收起回复

下载排行榜

全部1条评论

快来发表一下你的评论吧 !