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74HC595 pdf datasheet
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格式:rar |
大小:133 |
2008-08-06
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MM54HC595/MM74HC595
8-Bit Shift Registers with Output Latches
General Description
This high speed shift register utilizes advanced silicon-gate
CMOS technology. This device possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits, as well as the ability to drive 15 LS-TTL
loads.
This device contains an 8-bit serial-in, parallel-out shift register
that feeds an 8-bit D-type storage register. The storage
register has 8 TRI-STATEÉ outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge triggered
clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Features
Y Low quiescent current: 80 mA maximum (74HC Series)
Y Low input current: 1 mA maximum
Y 8-bit serial-in, parallel-out shift register
with storage
Y Wide operating voltage range: 2V±6V
Y Cascadable
Y Shift register has direct clear
Y Guaranteed shift frequency: DC to 30 MHz
8-Bit Shift Registers with Output Latches
General Description
This high speed shift register utilizes advanced silicon-gate
CMOS technology. This device possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits, as well as the ability to drive 15 LS-TTL
loads.
This device contains an 8-bit serial-in, parallel-out shift register
that feeds an 8-bit D-type storage register. The storage
register has 8 TRI-STATEÉ outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge triggered
clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Features
Y Low quiescent current: 80 mA maximum (74HC Series)
Y Low input current: 1 mA maximum
Y 8-bit serial-in, parallel-out shift register
with storage
Y Wide operating voltage range: 2V±6V
Y Cascadable
Y Shift register has direct clear
Y Guaranteed shift frequency: DC to 30 MHz
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