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A 600-MHz VLIW DSP
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2010-06-27
王杰
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Abstract—A 600-MHz VLIWdigital signal processor (DSP) de-
livers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply ac-
cumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M
transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200
mWat 300MHZ and 0.9 V. It has an eight-way VLIWDSP core, a
two-level memory system, and an I/O bandwidth of 2.4 GB/s. The
chip integrates a c64X DSP core with Viterbi and turbo decoders.
Architectural and circuit design approaches to achieve high perfor-
mance and low power using a semi-custom standard cell method-
ology, while maintaining backward compatibility, are described.
The chip is implemented in a 0.13- m CMOS process with six
layers of copper interconnect.
livers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply ac-
cumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M
transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200
mWat 300MHZ and 0.9 V. It has an eight-way VLIWDSP core, a
two-level memory system, and an I/O bandwidth of 2.4 GB/s. The
chip integrates a c64X DSP core with Viterbi and turbo decoders.
Architectural and circuit design approaches to achieve high perfor-
mance and low power using a semi-custom standard cell method-
ology, while maintaining backward compatibility, are described.
The chip is implemented in a 0.13- m CMOS process with six
layers of copper interconnect.
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