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Research Article The Chameleon
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2010-06-29
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Gerard J.M. Smit,
1 Andr ´ e B. J. Kokkeler,
1 Pascal T.Wolkotte,
1 Philip K. F. H¨ olzenspies,
1
Marcel D. van de Burgwal,
1 and PaulM. Heysters2
1
Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, Drienerlolaan 5,
7522 NB Enschede, The Netherlands
2
Recore Systems, Capitool 22, 7521 PL Enschede, The Netherlands
Received 15 May 2006; Revised 20 December 2006; Accepted 20 December 2006
Recommended by Neil Bergmann
We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at
a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient
and fault tolerant.We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile
processor called Montium. This reconfigurable processor has a small footprint (1.8mm2
in a 130 nm process), is power efficient
and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200
tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a
network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types
of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The
NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled
architecture, we introduce a run-time mapping tool.
Copyright © 2007 Gerard J. M. Smit et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly
cited.
1 Andr ´ e B. J. Kokkeler,
1 Pascal T.Wolkotte,
1 Philip K. F. H¨ olzenspies,
1
Marcel D. van de Burgwal,
1 and PaulM. Heysters2
1
Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, Drienerlolaan 5,
7522 NB Enschede, The Netherlands
2
Recore Systems, Capitool 22, 7521 PL Enschede, The Netherlands
Received 15 May 2006; Revised 20 December 2006; Accepted 20 December 2006
Recommended by Neil Bergmann
We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at
a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient
and fault tolerant.We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile
processor called Montium. This reconfigurable processor has a small footprint (1.8mm2
in a 130 nm process), is power efficient
and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200
tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a
network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types
of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The
NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled
architecture, we introduce a run-time mapping tool.
Copyright © 2007 Gerard J. M. Smit et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly
cited.
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