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GC1115 Daughterboard EVM
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2010-07-08
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The GC1115 Daughterboard and GC101 EVM comprise a two-part daughterboard and
motherboard used for demonstrating the GC1115 CFR. The GC1115 Daughterboard
hardware is a plug-in board to the GC101 EVM.
The GC1115 is a flexible, programmable, wideband crest factor reduction (CFR)
processor with a maximum composite bandwidth of 20 MHZ. The GC1115 selectively
reduces the peak-to-average ratio (PAR) of wideband digital signals provided in
quadrature (I & Q) format, such as those used in third-generation (3G) code division
multiple access (CDMA) wireless applications. Reducing the PAR of digital signals can
improve the efficiency of follow-on power amplifiers (PAs), ease the D/A converter
requirements and eliminate the out-of-band spectral regrowth caused by simple hard
limiting.
This document will describe the hardware portion of the GC1115 and its interface to the
GC101 EVM. More information about the GC101 EVM can be found in the GC101 EVM
User's Guide. Figure 1-1 is a high level block diagram of the GC101 and the interface it
provides to the GC1115. Figure 1-2 is a block diagram of the GC1115 Daughterboard.
motherboard used for demonstrating the GC1115 CFR. The GC1115 Daughterboard
hardware is a plug-in board to the GC101 EVM.
The GC1115 is a flexible, programmable, wideband crest factor reduction (CFR)
processor with a maximum composite bandwidth of 20 MHZ. The GC1115 selectively
reduces the peak-to-average ratio (PAR) of wideband digital signals provided in
quadrature (I & Q) format, such as those used in third-generation (3G) code division
multiple access (CDMA) wireless applications. Reducing the PAR of digital signals can
improve the efficiency of follow-on power amplifiers (PAs), ease the D/A converter
requirements and eliminate the out-of-band spectral regrowth caused by simple hard
limiting.
This document will describe the hardware portion of the GC1115 and its interface to the
GC101 EVM. More information about the GC101 EVM can be found in the GC101 EVM
User's Guide. Figure 1-1 is a high level block diagram of the GC101 and the interface it
provides to the GC1115. Figure 1-2 is a block diagram of the GC1115 Daughterboard.
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