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SN74LV374AT,pdf(OCTAL EDGE TRI
消耗积分:2 |
格式:rar |
大小:633 |
2010-07-27
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OR PW PACKAGE
P VIEW)
20
19
18
17
16
15
VCC
8Q
8D
7D
7Q
6Q
RGY PACKAGE
(TOP VIEW)
120
2
3
4
19
18
17
8Q
8D
7D
7Q
1Q
1D
2D
2Q
OE
VCC
The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff
. The Ioff
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
P VIEW)
20
19
18
17
16
15
VCC
8Q
8D
7D
7Q
6Q
RGY PACKAGE
(TOP VIEW)
120
2
3
4
19
18
17
8Q
8D
7D
7Q
1Q
1D
2D
2Q
OE
VCC
The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff
. The Ioff
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
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