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DS90CR218A,pdf datasheet (+3.3
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大小:552 |
2009-10-14
vinww特烦恼
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The DS90CR218A receiver deserializes three input LVDS
data streams into 21 bits of CMOS/TTL output data. When
operating at the maximum input clock rate of 85 Mhz, the
LVDS data is received at 595 Mbps per data channel for a
total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR218A is
an ideal means to solve EMI and cable size problems associated
with wide, high-speed TTL interfaces.
data streams into 21 bits of CMOS/TTL output data. When
operating at the maximum input clock rate of 85 Mhz, the
LVDS data is received at 595 Mbps per data channel for a
total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR218A is
an ideal means to solve EMI and cable size problems associated
with wide, high-speed TTL interfaces.
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