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RM42x Microcontroller
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The STREXD instruction should work in Thumb mode when Rt and Rt2 are the sameregister.The ARM Architecture permits the Thumb STREXD instruction to be encoded with thesame register used for both transfer registers （Rt and Rt2）。 Because of this erratum， theCortex-R4 processor treats such an encoding as UNPREDICTABLE and executes it as aNOP.This occurs when the processor is in Thumb state and a STREXD instruction isexecuted which has Rt = Rt2. This instruction was new in ARM Architecture version 7（ARMv7）。 It is not present in ARMv6T2 or other earlier architecture versions.If this occurs the destination register， Rd， which indicates the status of the instruction， isnot updated and no memory transaction takes place. If the software is attempting toperform an exclusive read-modify-write sequence， then it might either incorrectlycomplete without memory being written， or loop forever attempting to complete thesequence.This can be avoided by using two different registers for the data to be transferred by aSTREXD instruction. This may involve copying the data in the transfer register to asecond， different register for use by the STREX
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