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AD5669R FMC-SDP转接器和评估板/Xilinx KC705参考设计

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This version (09 Jan 2021 00:51) was approved by Robin Getz.The Previously approved version (01 Oct 2013 08:50) is available.Diff

Table of Contents

AD5669R FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

Supported Devices

Evaluation Boards

Overview

This document presents the steps to setup an environment for using the EVAL-AD5669RSDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5669RSDZ Evaluation Board with the Xilinx KC705 board.

ad5669.jpg

For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:

  • 1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
  • 2. The component SDP compatible product evaluation board
  • 3. Corresponding PC software ( shipped with the product evaluation board)

The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.

Note: it is expected that the analog performance on the two platforms may differ.

28 Sep 2012 10:32 · Adrian Costina

Below is presented a picture of SDP-B Controller Board with the EVAL-AD5669RSDZ Evaluation Board.

The AD5669R device is low power, octal, 16-bit, buffered voltage-output DAC. Device is guaranteed monotonic by design. The AD5669R has an on-chip reference with an internal gain of 2. The AD5669R-1 has a 1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V. The AD5669R-2/AD5669R-3 have a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V depending on the option selected. Devices with 1.25 V reference selected operate from a single 2.7 V to 5.5 V supply. Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5669R-1/AD5669R-2) or midscale (AD5669R-3) and remains powered up at this level until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 400 nA at 5 V and provides software-selectable output loads while in power-down mode for any or all DAC channels.

The EVAL-AD5669R evaluation board is designed to help customers quickly prototype new AD5669R circuits and reduce design time. To power the AD5669R evaluation board supply 5V between the AVDD and AGND inputs for the analog supply.

More information

Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Required Hardware

Required Software

  • Xilinx ISE 14.6.
  • UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200.
  • The EVAL-AD5669R reference project for Xilinx KC705 FPGA.

Downloads



Run the Demonstration Project

Hardware setup


Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.

  • Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
  • Connect the JTAG and UART cables to the KC705 and power up the FPGA board.


To power on the EVAL-AD5669R evaluation board, you need to provide +5V supply voltage to J2 connector on the board.

Reference Project Overview

The following commands were implemented in this version of EVAL-AD5669R reference project for Xilinx KC705 FPGA board.

Command Description
help? Displays all available commands.
reset! Makes a power-on reset.
powerMode= Selects a given power mode for selected DAC. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
power mode:
0 - normal operation.
1 - 1KOhm to GND.
2 - 100KOhms to GND.
3 - three-state.
powerMode? Displays the power mode for one selected DAC. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
intRef= Turns on/off the internal reference. Accepted values:
0 - turns off the internal reference.
1 - turns on the internal reference.
intRef? Displays the status of the internal reference.
loadN= Loads selected DAC register with a given value. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
15 - all DACs.
value:
0 .. 65535 - value to be written in register.
updateN Updates the selected DAC with the last value written in register. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
15 - all DACs.
value:
0 .. 65535 - value to be written in register.
loadNUpdateN Loads and updates the selected DAC with a given value. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
15 - all DACs.
value:
0 .. 65535 - value to be written in register.
loadNUpdateAll Loads the selected DAC with a given value and updates all DACs. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
15 - all DACs.
value:
0 .. 65535 - value to be written in register.
enLdacPin= Enables/Disables the LDAC pin for selected DAC. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
value:
1 - disable LDAC pin.
0 - enable LDAC pin.
enLdacPin? Displays the status(enabled or disabled) of the LDAC pin for a selected DAC. Accepted values:
channel:
0 .. 7 - selected DAC A .. H.
clrCode= Loads Clear Code Register with specific clear code.
Accepted values:
0 - clears code to zero scale when CLR pin goes from high to low.
1 - clears code to midscale when CLR pin goes from high to low.
2 - clears code to full scale when CLR pin goes from high to low.
3 - no operation.
clrCode? Displays the active clear code.
ldacPin= Sets the output value of LDAC pin. Accepted values:
0 - sets LDAC pin low.(default)
1 - sets LDAC pin high.
ldacPin? Displays the value of LDAC pin.
clrPin= Sets the output value of CLR pin. Accepted values:
0 - sets CLR pin low.
1 - sets CLR pin high.(default)
clrPin? Displays the value of CLR pin.

Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.

The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. terminal_kc705.jpg

Software Project Setup

The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design:

Github Repository

  • From this entire repository you will use cf_sdp_kc705 folder. This is common for all KC705 projects.

EDK KC705 project

  • Open the Xilinx SDK. When the SDK starts, it asks you to provide a folder where to store the workspace. Any folder can be provided. Make sure that the path where it is located does not contain any spaces.
  • In the SDK select the File→Import menu option to import the software projects into the workspace.

Import Projects

  • In the Import window select the General→Existing Projects into Workspace option.

Existing Projects Import

  • In the Import Projects window select the cf_sdp_kc705 folder as root directory and check the Copy projects into workspace option. After the root directory is chosen the projects that reside in that directory will appear in the Projects list. Press Finish to finalize the import process.

Projects Import

  • The Project Explorer window now shows the projects that exist in the workspace without software files.

Project Explorer

  • Now the software must be added in your project. For downloading the software, you must use 3 links from Github given in Downloads section. From there you'll download the specific driver, the specific commands and the Xilinx Boards Common Drivers(which are commons for all Xilinx boards). All the software files downloaded must be copied in src folder from sw folder.

Project complete

  • Before compilation in the file called Communication.h you have to uncomment the name of the device that you currently use. In the picture below there is an example of this, which works only with AD5629R project. For another device, uncomment only the respective name. You can have one driver working on multiple devices, so the drivers's name and the uncommented name may not be the same for every project.

Communication.h

  • The SDK should automatically build the project and the Console window will display the result of the build. If the build is not done automatically, select the Project→Build Automatically menu option.
  • If the project was built without any errors, you can program the FPGA and run the software application.
13 Aug 2013 09:22 · Lucian Sin

More information

28 May 2012 15:18
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