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PCI2031 pdf datasheet (PCI-to-
消耗积分:5 |
格式:rar |
大小:333 |
2009-02-17
王强
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The TI PCI2031 PCI-to-PCI bridge provides a high-performance connection path between two peripheral
component interconnect (PCI) buses. Transactions can occur between a master on one PCI bus and a target
on another PCI bus. The bridge supports burst-mode transfers to maximize data throughput, and the two bus
traffic paths through the bridge act independently.
The PCI2031 bridge is compliant with the PCI Local Bus Specification 2.1, and can be used to overcome the
electrical loading limit of ten devices per PCI bus by creating hierarchical buses. Furthermore, add-in cards
requiring multiple PCI devices can use the bridge to overcome the electrical loading limit of one PCI device
per slot.
The PCI2031 bridge is also compliant with the PCI-to-PCI Bridge Specification 1.0, and implements many
additional features that make it an ideal solution for bridging two PCI buses. It can be configured for subtractive
decoding, and negative decoding can be disabled on the secondary interface. Two extension windows are also
included for special decoding purposes. The serial- and parallel-port addresses can also be programmed for
positive decoding on the primary interface. The bridge implements many other features, listed above, that add
performance and flexibility.
An advanced CMOS process is utilized to achieve low system-power consumption while operating at PCI clock
rates up to 33 MHz.
component interconnect (PCI) buses. Transactions can occur between a master on one PCI bus and a target
on another PCI bus. The bridge supports burst-mode transfers to maximize data throughput, and the two bus
traffic paths through the bridge act independently.
The PCI2031 bridge is compliant with the PCI Local Bus Specification 2.1, and can be used to overcome the
electrical loading limit of ten devices per PCI bus by creating hierarchical buses. Furthermore, add-in cards
requiring multiple PCI devices can use the bridge to overcome the electrical loading limit of one PCI device
per slot.
The PCI2031 bridge is also compliant with the PCI-to-PCI Bridge Specification 1.0, and implements many
additional features that make it an ideal solution for bridging two PCI buses. It can be configured for subtractive
decoding, and negative decoding can be disabled on the secondary interface. Two extension windows are also
included for special decoding purposes. The serial- and parallel-port addresses can also be programmed for
positive decoding on the primary interface. The bridge implements many other features, listed above, that add
performance and flexibility.
An advanced CMOS process is utilized to achieve low system-power consumption while operating at PCI clock
rates up to 33 MHz.
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