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基于FPGA的PCI硬件加解密卡设计
消耗积分:10 |
格式:rar |
大小:617 |
2011-01-07
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提出一种基于FPGA的PCI硬件加解密卡的设计方案，用硬件加解密取代了传统的软件加解密，将加解密模块和PCI接口模块集成在一个FPGA芯片内实现。分析了PCI加解密卡的软硬件的结构和原理，详细介绍了DESX加解密算法的原理、步骤和硬件实现、PCI接口模块的IP核设计以及USB接口模块的电路连接。系统硬件以FPGA为核心，使用QuartusⅡ7.2软件和VHDL语言设计，软件由DriverStudio2.7和Visual C++6.0设计。采用192位密钥的DESX分组对称加解密算法来取代64位DES算法，密文和密钥在专用硬件中存储，计算机内只有明文，有效防止黑客攻击，保护数据安全。设计采用逻辑综合式取代时钟驱动级联式来实现DESX算法，使加密一组数据的时间由16个周期缩短为1个周期。
- Abstract:
- A design proposal of hardware encryption and decryption PCI board based on FPGA was presented. Hardware encryption and decryption was used to replace the traditional software encryption and decryption. The encryption and decryption module and PCI IP core were integrated into FPGA chip. The structure and principle of software and hardware of enryption and decryption PCI board were analyzed，the principle，steps and the hardware implementation of DESX，PCI IP Core and the circuit connection of USB interface module were introduced. System hardware focusing on FPGA was designed with Quartus Ⅱ7.2 and VHDL language，software was designed with DriverStudio2.7 and Visual C++6.0. The DESX with 192bit key was adopted to replace DES with 64bit key. Ciphertext and secret key were stored in spicific hardware，only plaintext was stored in PC，this design could effectively protect data security from hacker attack. Logic synthesis was adopted to realize DESX to replace clock driving cascade， the time of handling one set data was cut short from 16 periods to 1 period.
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