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Testing and specifying FAST lo
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2009-03-30
孙成红
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FASTE is a second generation Schottky logic family that utilizes
advanced oxide-isolation techniques to increase the speed and
decrease the power dissipation beyond the levels achievable with
conventional junction isolated families. The improved performance
of the family is exhibited in two ways — first, the speed and power
characteristics of the devices are improved, and second, the
conditions under which speed and power are specified are much
tighter. For instance, LS and S TTL families offer AC limits only at a
nominal +5.00V VCC supply voltage and at room temperature, 25°C.
By contrast, FAST guarantees improved AC performance and
specifies that performance over a supply variation of +5.00V ±10%
and at temperatures from 0°C to 70°C. Thus the designer no longer
needs to derate his propagation delays from the data sheet limits to
compensate for speed degradation over the temperature range.
With every advance of this magnitude, there arise new
considerations that must be kept in mind both by the system
designer and the user setting up test procedures. FAST is no
exception, and it is these considerations that will be addressed in
this application note. This paper represents an attempt to describe
the way the FAST logic parts are specified, why they are specified in
the way they are, and how the parts may be tested in the
qualification lab and at incoming inspection to verify their
performance.
advanced oxide-isolation techniques to increase the speed and
decrease the power dissipation beyond the levels achievable with
conventional junction isolated families. The improved performance
of the family is exhibited in two ways — first, the speed and power
characteristics of the devices are improved, and second, the
conditions under which speed and power are specified are much
tighter. For instance, LS and S TTL families offer AC limits only at a
nominal +5.00V VCC supply voltage and at room temperature, 25°C.
By contrast, FAST guarantees improved AC performance and
specifies that performance over a supply variation of +5.00V ±10%
and at temperatures from 0°C to 70°C. Thus the designer no longer
needs to derate his propagation delays from the data sheet limits to
compensate for speed degradation over the temperature range.
With every advance of this magnitude, there arise new
considerations that must be kept in mind both by the system
designer and the user setting up test procedures. FAST is no
exception, and it is these considerations that will be addressed in
this application note. This paper represents an attempt to describe
the way the FAST logic parts are specified, why they are specified in
the way they are, and how the parts may be tested in the
qualification lab and at incoming inspection to verify their
performance.
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