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Metastability tests for the 74
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2009-03-30
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Under contract with Signetics, Mr. Thomas J. Chaney of Washington
University, St. Louis tested a set of nineteen 74F786 samples
(packages) to determine the metastable state recovery statistics for
the circuits. The tests were conducted using a procedure described
in a paper entitled “Characterization and Scaling of MOS Flip-Flop
Performance”, (section IV), by T. Chaney and F. Rosenberger,
presented at the CalTech Conference on VLSI, January 1979. The
general test procedure was to test all 19 packages under one
condition, then test the best, worst, and an average package in more
detail. According to Mr. Chaney, the test results from the 19
packages formed one of the tightest groupings that he has ever
seen. As the parts were numbered, package No. 7 had the fastest
resolving times, No. 11 produced some of the slowest resolving
times, and No. 1 had resolving times near the middle of the test
results. This ranking of the test results from 3 packages remained
the same throughout the balance of the test program, which
supports the complete testing of only 3 packages. In general, the
poorest performance resulted when the packages were heated to
near 75°C with VCC = 4.5VDC and the best performance resulted
when the packages were cooled to near 0°C with VCC = 5.5VDC.
The variation within one package caused by the temperature and
VCC changes was greater than the variation from package to
package. It must be noted that none of the packages tested even
approached the data sheet input to output worst case propagation
delay of 10.5ns. All the packages tested for a single active output,
had propagation delays of about 6ns. Typically, the parts with longer
propagation delays also have slower resolving times. Thus, one
would expect that the delay time needed to have only one failure in
32 years using a 10ns propagation delay part would be much longer
than a value derived from just adding 10–6 = 4ns to the above
calculations. thus it appears that the poorest performance measured
in this study should be considered a measurement at the edge of the
typical range for 74F786 parts.
It must also be noted that the tight grouping of this set of packages
means that, when comparing differences between these test results,
the measured error, as outlined in “Measured Flip-Flop Responses
to Marginal Triggering”, IEETC, December 1983, is significant. This
is illustrated in association with Table 5.
University, St. Louis tested a set of nineteen 74F786 samples
(packages) to determine the metastable state recovery statistics for
the circuits. The tests were conducted using a procedure described
in a paper entitled “Characterization and Scaling of MOS Flip-Flop
Performance”, (section IV), by T. Chaney and F. Rosenberger,
presented at the CalTech Conference on VLSI, January 1979. The
general test procedure was to test all 19 packages under one
condition, then test the best, worst, and an average package in more
detail. According to Mr. Chaney, the test results from the 19
packages formed one of the tightest groupings that he has ever
seen. As the parts were numbered, package No. 7 had the fastest
resolving times, No. 11 produced some of the slowest resolving
times, and No. 1 had resolving times near the middle of the test
results. This ranking of the test results from 3 packages remained
the same throughout the balance of the test program, which
supports the complete testing of only 3 packages. In general, the
poorest performance resulted when the packages were heated to
near 75°C with VCC = 4.5VDC and the best performance resulted
when the packages were cooled to near 0°C with VCC = 5.5VDC.
The variation within one package caused by the temperature and
VCC changes was greater than the variation from package to
package. It must be noted that none of the packages tested even
approached the data sheet input to output worst case propagation
delay of 10.5ns. All the packages tested for a single active output,
had propagation delays of about 6ns. Typically, the parts with longer
propagation delays also have slower resolving times. Thus, one
would expect that the delay time needed to have only one failure in
32 years using a 10ns propagation delay part would be much longer
than a value derived from just adding 10–6 = 4ns to the above
calculations. thus it appears that the poorest performance measured
in this study should be considered a measurement at the edge of the
typical range for 74F786 parts.
It must also be noted that the tight grouping of this set of packages
means that, when comparing differences between these test results,
the measured error, as outlined in “Measured Flip-Flop Responses
to Marginal Triggering”, IEETC, December 1983, is significant. This
is illustrated in association with Table 5.
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