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循环过滤器配置为MAX3670低抖动PLL频率参考时钟发生器

消耗积分:3 | 格式:rar | 大小:52 | 2009-04-22

吴湛

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Abstract: The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses an external high-Q voltage-controlled oscillator (VCO) to create a very low jitter clock signal phase-locked to a system clock input. It is ideal for SONET OC-48 or OC-192 applications requiring a very low jitter 156 MHZ or 622MHz clock signal. When used with a low-jitter voltage-controlled SAW oscillator (VCSO) or a voltage-controlled crystal oscillator (VCX), the total system jitter can be less than 1 psrms. This design note provides analysis and examples that address optimal PLL configuration, including external component values, internal divider settings, and internal phase detector gain for low-jitter applications.
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