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介绍CoolRunner系列XPLA3 CPLD器件的宏单元
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大小:330 |
2009-05-13
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Xilinx CoolRunner XPLA3 CPLDs provide designers with several useful configuration options
for each macrocell. These options allow greater flexibility when creating complex designs.
Some of the configurations available are: data register (D, T, and Latch), input register, buried
combinatorial or registered node, and I/O port. Combinations of these configurations can be
used to increase macrocell utilization.
In addition to better macrocell utilization, the XPLA3 input registers have a very short setup
time. This feature is beneficial when data transfers between devices on a board must occur
within one clock cycle.
for each macrocell. These options allow greater flexibility when creating complex designs.
Some of the configurations available are: data register (D, T, and Latch), input register, buried
combinatorial or registered node, and I/O port. Combinations of these configurations can be
used to increase macrocell utilization.
In addition to better macrocell utilization, the XPLA3 input registers have a very short setup
time. This feature is beneficial when data transfers between devices on a board must occur
within one clock cycle.
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