With the possible exceptions of speed, deterministic timing, and low power, few things are as important to programmable logic designers as reconfigurability and available I/O. In-System Programming (ISP) has provided a flexible means of reconfigurability, but this feature mandates the availability of at least four pins to accommodate ISP and Boundary Scan operations. Some ISP devices provide dual configurations of the JTAG pins, where the ISP pins may be configured as general purpose I/O if not required for ISP or Boundary Scan. In most cases, however, the designation of JTAG pins as I/O precludes this device from future ISP operations unless the part is bulk erased using a VPP mode of erasure. Historically, the use of ISP techniques exacerbated the issue of insufficient device I/O, especially for smaller devices with low I/O counts.