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基于FPGA 的GPS高精度短时标设计
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2009-06-16
张杰
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鉴于短时标在航天、电子及电力系统中的需求，本文阐述了以FPGA 为主处理器对GPS 接收机进行数据采集处理，提供高精度短时标及短时标对应的时间码相关信息。为了确保时标的精度，减少时间信息解码过程中的采样误差，从方法、设计两方面考虑，采取了一系列的措施，保证了时标设计的精度。
关键词：短时标；GPS 接收机；FPGA；多时钟域处理；
Abstract: the thesis expatiated digital collection and processing for GPS receiver based on FPGA used as master processor, providing short timing scale accurately and information related with timing code. The system adopted a series of measures considering from means to design and supported the precision of design, for decreasing the collection error in the process of timing decoding and ensuring the precision of timing.
Keyword: short timing scale；GPS receiver; FPGA; multiple clock processing;
关键词：短时标；GPS 接收机；FPGA；多时钟域处理；
Abstract: the thesis expatiated digital collection and processing for GPS receiver based on FPGA used as master processor, providing short timing scale accurately and information related with timing code. The system adopted a series of measures considering from means to design and supported the precision of design, for decreasing the collection error in the process of timing decoding and ensuring the precision of timing.
Keyword: short timing scale；GPS receiver; FPGA; multiple clock processing;
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