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ADF4001,pdf datasheet (200 MHz
消耗积分:5 |
格式:rar |
大小:500 |
2009-09-16
欲望都市
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The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REFIN
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an external
loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REFIN
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an external
loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
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