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RDD104 pdf datasheet
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2008-07-18
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DESCRIPTION OF OPERATION:
The RDD104 is a CMOS four decade
divider circuit that advances on each negative
transition of the input clock pulse. When the reset
input is high the circuit is cleared to zero. The
clock input is applied to a three stage inverting
amplifier network whose output is brought out so
that an external crystal network can be used to
form an oscillator circuit. If the clock output is not
used,the amplifier acts as an input buffer. Two
select inputs are provided which enables the circuit
to divide by 10, 100, 1,000 or 10,000.
The RDD104 is a CMOS four decade
divider circuit that advances on each negative
transition of the input clock pulse. When the reset
input is high the circuit is cleared to zero. The
clock input is applied to a three stage inverting
amplifier network whose output is brought out so
that an external crystal network can be used to
form an oscillator circuit. If the clock output is not
used,the amplifier acts as an input buffer. Two
select inputs are provided which enables the circuit
to divide by 10, 100, 1,000 or 10,000.
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