These NOR and NAND gates are monolithic complementa-ry MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical cir- cuit with output swings essentially equal to the supply volt-age. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leak-age current is consumed during static conditions. All inputs are protected against static discharge and latching condi-tions
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