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SN54ABT853, SN74ABT853,pdf98-B
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The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs.
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