The next generation computer and communication systems now being developed will handle data rates of multiple gigabits/sec- ond. Many systems will incorporate processors and SERDES chip sets that exceed GigaHertz clock frequencies. New and troubling input/output issues are emerging as switches, routers, server blades, and storage area networking equipment moving toward 10 Gbps data rates. Digital design engineers choosing chip-to-chip and backplane technologies for these systems are finding signal integrity challenges that have not been encountered before.