This amplifier circuit contains four 30-dB logarithmic stages. Gain in each stage is such that the output of each stage is proportional to the logarithm of the input voltage over the 30-dB input voltage range. Each half of the circuit contains two of these 30-dB stages summed together in one
differential output that is proportional to the sum of the logarithms of the input voltages of the two stages. The four stages may be interconnected to obtain a theoretical input voltage range of 120-dB. In practice, this permits the input voltage range typically to be greater than 80-dB with log linearity of ± 0.5-dB (see application data). Bandwidth is from dc to 40 MHz.
This circuit is useful in data compression and analog compensation.
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