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Xilinx三重模块冗余(TMR)开发工具TMRTool
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The Xilinx TMR methodology, along with scrubbing, provides full single-event upset
(SEU ) and single-event transient (SET ) immunity for any Virtex® FPGA design. In
addition, the TMRT ool:
• Supports Windows 2000/XP with ISE ™ 6.3i, 7.1i, 8.2i and 9.2i tools, all design
entry methods, HDL , and synthesis tools
• Provides optional SRL 16 extraction and optional half-latch extraction capability
• Increases productivity by reducing errors, speeding TMR implementation, and
enabling easy integration of custom-built TMR modules while giving designers
complete control over how their design is triplicated
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