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介绍在XPLA3器件中执行在系统编程操作
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2009-05-13
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With the possible exceptions of speed, deterministic timing, and low power, few things are as
important to programmable logic designers as reconfigurability and available I/O. In-System
Programming (ISP) has provided a flexible means of reconfigurability, but this feature mandates
the availability of at least four pins to accommodate ISP and Boundary Scan operations. Some
ISP devices provide dual configurations of the JTAG pins, where the ISP pins may be
configured as general purpose I/O if not required for ISP or Boundary Scan. In most cases,
however, the designation of JTAG pins as I/O precludes this device from future ISP operations
unless the part is bulk erased using a VPP mode of erasure. Historically, the use of ISP
techniques exacerbated the issue of insufficient device I/O, especially for smaller devices with
low I/O counts.
Xilinx XPLA3 devices provide designers with a Port Enable pin, which both facilitates ISP and
provides a maximum number of I/O pins for any given macrocell count XPLA3 CPLD. This pin
serves as a control pin which may redirect JTAG pins that were previously configured as I/O.
The use of this feature requires very little external circuitry to provide for the dual capability of
JTAG pins as I/O.
important to programmable logic designers as reconfigurability and available I/O. In-System
Programming (ISP) has provided a flexible means of reconfigurability, but this feature mandates
the availability of at least four pins to accommodate ISP and Boundary Scan operations. Some
ISP devices provide dual configurations of the JTAG pins, where the ISP pins may be
configured as general purpose I/O if not required for ISP or Boundary Scan. In most cases,
however, the designation of JTAG pins as I/O precludes this device from future ISP operations
unless the part is bulk erased using a VPP mode of erasure. Historically, the use of ISP
techniques exacerbated the issue of insufficient device I/O, especially for smaller devices with
low I/O counts.
Xilinx XPLA3 devices provide designers with a Port Enable pin, which both facilitates ISP and
provides a maximum number of I/O pins for any given macrocell count XPLA3 CPLD. This pin
serves as a control pin which may redirect JTAG pins that were previously configured as I/O.
The use of this feature requires very little external circuitry to provide for the dual capability of
JTAG pins as I/O.
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