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CDP1879和CDP1879C1实时时钟的设计指南
消耗积分:3 |
格式:rar |
大小:333 |
2009-05-19
吴湛
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The CDP1879 and CDP1879C1 Real-Time Clocks [1] are 24
pin devices, each consisting essentially of a long string of
counters that supply standard clock time and date information
in BCD format, Figure 1. In addition, the CDP1879
features an alarm circuit that activates the interrupt output
pin and a separate clock output pin that provides a programmable
square-wave output signal. Both the internal-alarm
and clock-out signals can trigger the interrupt output pin, so
that a status register is available to indicate the interrupt
source. Users can supply a signal to the power-down pin
that allows the interrupt-output pin level to control external
power-down and wake-up circuits. Software generally
required by other real-time clocks to prevent clock rollover is
eliminated by a transparent “freeze” circuit that assures data
integrity when accessing the clock. The clock’s counters,
plus a control register that regulates operation, are
individually selectable using three address lines. Internal
control signals governing read and write operations are
selected through the IO/MEM pin, which places the device in
a memory-mapped or I/O-mapped mode of operation.
pin devices, each consisting essentially of a long string of
counters that supply standard clock time and date information
in BCD format, Figure 1. In addition, the CDP1879
features an alarm circuit that activates the interrupt output
pin and a separate clock output pin that provides a programmable
square-wave output signal. Both the internal-alarm
and clock-out signals can trigger the interrupt output pin, so
that a status register is available to indicate the interrupt
source. Users can supply a signal to the power-down pin
that allows the interrupt-output pin level to control external
power-down and wake-up circuits. Software generally
required by other real-time clocks to prevent clock rollover is
eliminated by a transparent “freeze” circuit that assures data
integrity when accessing the clock. The clock’s counters,
plus a control register that regulates operation, are
individually selectable using three address lines. Internal
control signals governing read and write operations are
selected through the IO/MEM pin, which places the device in
a memory-mapped or I/O-mapped mode of operation.
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