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PC100同步动态RAM与JEDEC标准的定时参数的比较
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格式:rar |
大小:22 |
2009-05-21
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The 100MHz SDRAM was designed to improve
memory bandwidth. It synchronizes the internal
operation of the DRAM to a system clock to achieve
higher memory bandwidth per pin by pipelining internal
operations. It includes multiple independent
memory banks to allow the user to hide access and
precharge latency, provided that the system can
ping-pong between the banks when a new row is
opened or closed. This device improves noise
immunity to input receivers by essentially ignoring
the input pins completely, except during a narrow
setup and hold window around the rising edge of the
system clock. The device includes a mode register
to allow the user to optimize the pipeline length of
the device in order to minimize the read to output
delay based on the users operating clock frequency.
A self refresh mode which was normally offered on
more expensive low power EDO devices, is provided
as standard equipment.
memory bandwidth. It synchronizes the internal
operation of the DRAM to a system clock to achieve
higher memory bandwidth per pin by pipelining internal
operations. It includes multiple independent
memory banks to allow the user to hide access and
precharge latency, provided that the system can
ping-pong between the banks when a new row is
opened or closed. This device improves noise
immunity to input receivers by essentially ignoring
the input pins completely, except during a narrow
setup and hold window around the rising edge of the
system clock. The device includes a mode register
to allow the user to optimize the pipeline length of
the device in order to minimize the read to output
delay based on the users operating clock frequency.
A self refresh mode which was normally offered on
more expensive low power EDO devices, is provided
as standard equipment.
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