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xapp134 verilog源代码
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xapp134 verilog代码
The SDRAM controller is designed for the Virtex V300bg432-6. It's simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
1. Is RAS to CAS delay programmable?
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. No, the data registers has a fixed number of pipeline stages. This reference design supports RAS-to-CAS delay of 2 clock cycles. If you need to adjust to a different RAS-to-CAS delay, change the SRL16 Address values in sys_int.v. The address value should be (Trcd/Tck) +1
. Note, you still need to write the RAS-to-CAS value to the Controller's Mode Reg during PRECHARGE command. The value should be (Trcd/Tck) -2
2. How do I modify the design to support 128Mb/256Mb SDRAM parts with a 64-bit data bus?
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. You'll need to add more IO buffers for the extra data and address signals (in sdrm.v)
. You'll need to change ADDR_MSB and DATA_MSB (in define.v)
. In the current design, instead of 1 tristate signal for the Data lines,
we duplicate it to 4 signals, each having 8 loads.
This was done to reduce net delays on that tristate signal.
You may need to add 4 more tristate lines if you're going to 64-bit.
The tristate signal is sd_doe_n in sdrm.v
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