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74163 TTL可予制四位二进制同步清除计数器
消耗积分:5 |
格式:rar |
大小:176 |
2009-08-08
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These synchronous, presettable counters feature an internal
carry look-ahead for application in high-speed counting
designs. The 161 and 163 are 4-bit binary counters. The
carry output is decoded by means of a NOR gate, thus preventing
spikes during the normal counting mode of operation.
Synchronous operation is provided by having all flipflops
clocked simultaneously so that the outputs change coincident
with each other when so instructed by the countenable
inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the 161 is asynchronous; and a
low level at the clear input sets all four of the flip-flop outputs
low, regardless of the levels of clock, load, or enable
inputs. The clear function for the 163 is synchronous; and a
low level at the clear input sets all four of the flip-flop outputs
low after the next clock pulse, regardless of the levels
of the enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maximum
count desired can be accomplished with one
external NAND gate. The gate output is connected to the
clear input to synchronously clear the counter to all low outputs.
Low-to-high transitions at the clear input of the 163 are
also permissible, regardless of the logic levels on the clock,
enable, or load inputs.
The carry look-ahead circuitry provides for cascading counters
for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both countenable
inputs (P and T) must be high to count, and input T is
fed forward to enable the ripple carry output. The ripple carry
output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the QA output. This high-level overflow ripple carry pulse
can be used to enable successive cascaded stages. Highto-
low-level transitions at the enable P or T inputs of the 161
through 163 may occur, regardless of the logic level on the
clock.
carry look-ahead for application in high-speed counting
designs. The 161 and 163 are 4-bit binary counters. The
carry output is decoded by means of a NOR gate, thus preventing
spikes during the normal counting mode of operation.
Synchronous operation is provided by having all flipflops
clocked simultaneously so that the outputs change coincident
with each other when so instructed by the countenable
inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the 161 is asynchronous; and a
low level at the clear input sets all four of the flip-flop outputs
low, regardless of the levels of clock, load, or enable
inputs. The clear function for the 163 is synchronous; and a
low level at the clear input sets all four of the flip-flop outputs
low after the next clock pulse, regardless of the levels
of the enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maximum
count desired can be accomplished with one
external NAND gate. The gate output is connected to the
clear input to synchronously clear the counter to all low outputs.
Low-to-high transitions at the clear input of the 163 are
also permissible, regardless of the logic levels on the clock,
enable, or load inputs.
The carry look-ahead circuitry provides for cascading counters
for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both countenable
inputs (P and T) must be high to count, and input T is
fed forward to enable the ripple carry output. The ripple carry
output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the QA output. This high-level overflow ripple carry pulse
can be used to enable successive cascaded stages. Highto-
low-level transitions at the enable P or T inputs of the 161
through 163 may occur, regardless of the logic level on the
clock.
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