资料下载
×
csrGen: Automated_CSRs_for_ASIC/FPGA_Processor_Interfaces
消耗积分:1 |
格式:pdf |
大小:66KB |
2016-02-17
mezwooooo
分享资料个
csrGen is a tool to automatically produce synthesizable verilog RTL code for the registers that make up the memory map of a processor interface from a simple template that lists and describes the registers. Using a tool for registers speeds ASIC or FPGA development, avoids common errors, and can also aid documentation, verification, and firmware development.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
