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DS90CR287/DS90CR288A,pdf datas
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2009-10-14
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The DS90CR287 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CR288A receiver converts
the four LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency of 85
MHz, 28 bits of TTL data are transmitted at a rate of 595
Mbps per LVDS data channel. Using a 85 MHz clock, the
data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CR288A receiver converts
the four LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency of 85
MHz, 28 bits of TTL data are transmitted at a rate of 595
Mbps per LVDS data channel. Using a 85 MHz clock, the
data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
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