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DS90CR483A/DS90CR484A,pdf data
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2009-10-14
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The DS90CR483A transmitter converts 48 bits of CMOS/TTL
data into eight LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel
with the data streams over a ninth LVDS link. Every cycle
of the transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR484A receiver converts the LVDS
data streams back into 48 bits of CMOS/TTL data. At a transmit
clock frequency of 112MHz, 48 bits of TTL data are
transmitted at a rate of 672Mbps per LVDS data channel. Using
a 112MHz clock, the data throughput is 5.38Gbit/s (672Mbytes/
s).
data into eight LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel
with the data streams over a ninth LVDS link. Every cycle
of the transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR484A receiver converts the LVDS
data streams back into 48 bits of CMOS/TTL data. At a transmit
clock frequency of 112MHz, 48 bits of TTL data are
transmitted at a rate of 672Mbps per LVDS data channel. Using
a 112MHz clock, the data throughput is 5.38Gbit/s (672Mbytes/
s).
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