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LMH0031,pdf datasheet (Descram
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2009-10-14
刘满贵
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The LMH0031 SMPTE 292M / 259M Digital Video
Deserializer/Descrambler with Video and Ancillary Data
FIFOs is a monolithic integrated circuit that deserializes and
decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial
component video data, to 20-bit parallel data with a synchronized
parallel word-rate clock. It also deserializes and decodes
SMPTE 259M, 270Mbps, 360Mbps and
SMPTE 344M (proposed) 540Mbps serial component video
data, to 10-bit parallel data. Functions performed by the
LMH0031 include: clock/data recovery from the serial data,
serial-to-parallel data conversion, SMPTE standard data decoding,
NRZI-to-NRZ conversion, parallel data clock generation,
word framing, CRC and EDH data checking and handling,
Ancillary Data extraction and automatic video format
determination. The parallel video output features a variabledepth
FIFO which can be adjusted to delay the output data
up to 4 parallel data clock periods. Ancillary Data may be
selectively extracted from the parallel data through the use
of masking and control bits in the configuration and control
registers and stored in the on-chip FIFO. Reverse LSB dithering
is also implemented.
Deserializer/Descrambler with Video and Ancillary Data
FIFOs is a monolithic integrated circuit that deserializes and
decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial
component video data, to 20-bit parallel data with a synchronized
parallel word-rate clock. It also deserializes and decodes
SMPTE 259M, 270Mbps, 360Mbps and
SMPTE 344M (proposed) 540Mbps serial component video
data, to 10-bit parallel data. Functions performed by the
LMH0031 include: clock/data recovery from the serial data,
serial-to-parallel data conversion, SMPTE standard data decoding,
NRZI-to-NRZ conversion, parallel data clock generation,
word framing, CRC and EDH data checking and handling,
Ancillary Data extraction and automatic video format
determination. The parallel video output features a variabledepth
FIFO which can be adjusted to delay the output data
up to 4 parallel data clock periods. Ancillary Data may be
selectively extracted from the parallel data through the use
of masking and control bits in the configuration and control
registers and stored in the on-chip FIFO. Reverse LSB dithering
is also implemented.
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