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IEEE 1394 火线协议标准
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1394 Open Host Controller Interface or IEEE 1394 火线协议标准
Specification Release 1.1 January 6, 2000
The following documents may be useful in understanding the terms and concepts used in this specification. The documents
are for general background purposes only and are not incorporated into and do not form a part of this specification.
[A] IEEE 1394-1995 High Performance Serial Bus
IEEE, 1995
[B] ISO/IEC 13213:1994 Control and Status Register Architecture for Microcomputer Busses
International Standards Organization, 1994
[C] IEEE 1394a-2000
IEEE Standard for a High Performance Serial bus (Supplement)
All references to 1394 in this document refer to IEEE 1394-1995 ([A] above) unless otherwise specified.
Following IEEE conventions, the term “quadlet” is used throughout this document to specify a 32-bit word.
1.2 Overview
The 1394 Open Host Controller Interface (Open HCI) is an implementation of the link layer protocol of the 1394 Serial
Bus, with additional features to support the transaction and bus management layers. The 1394 Open HCI also includes
DMA engines for high-performance data transfer and a host bus interface.
IEEE 1394 (and the 1394 Open HCI) supports two types of data transfer: asynchronous and isochronous. Asynchronous
data transfer puts the emphasis on guaranteed delivery of data, with less emphasis on guaranteed timing. Isochronous data
transfer is the opposite, with the emphasis on the guaranteed timing of the data, and less emphasis on delivery.
1.2.1 Asynchronous functions
The 1394 Open HCI can transmit and receive all of the defined 1394 packet formats. Packets to be transmitted are read
out of host memory and received packets are written into host memory, both using DMA. The 1394 Open HCI can also
be programmed to act as a bus bridge between host bus and 1394 by directly executing 1394 read and write requests as
reads and writes to host bus memory space.Isochronous functions
The 1394 Open HCI is capable of performing the cycle master function as defined by 1394. This means it contains a cycle
timer and counter, and can queue the transmission of a special packet called a “cycle start” after every rising edge of the
8 kHz cycle clock. The 1394 Open HCI can generate the cycle clock internally (required) or use an external reference
(optional). When not the cycle master, the 1394 Open HCI keeps its internal cycle timer synchronized with the cycle
master node by correcting its own cycle timer with the reload value from the cycle start packet.
Conceptually, the 1394 Open HCI supports one DMA controller each for isochronous transmit and isochronous receive.
Each DMA controller may be implemented to support up to 32 different DMA channels, referred to as DMA contexts
within this document.
The isochronous transmit DMA controller can transmit from each context during each cycle. Each context can transmit
data for a single isochronous channel.
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AGE50S
2017-02-16
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