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Thermal transient characteriza
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2009-11-29
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Thermal transient characterization methodology for single-die and stacked structures:High-power semiconductor packages typically exhibit a
three-dimensional heat flow, resulting in large lateral changes
in chip and case surface temperature. For single-chip devices
we propose to use an unambiguous definition for the junctionto-
case thermal resistance as a key parameter, based on a transient
measurement technique with much higher repeatability
also for very low thermal resistances compared to a two-point
thermal resistance measurement. The technique is illustrated
on thermal transient measurements of power MOSFETs. A
comparison between different thermal coupling to the ambient
is used to demonstrate the method’s capability to reveal even
subtle internal details of the package. The concept is extended
to multi-chip and stacked-chip structures, where transfer impedances
have to be introduced. Here, the dynamic properties
of the package are important and complex impedance mapping
is the proper way to characterize the package.
three-dimensional heat flow, resulting in large lateral changes
in chip and case surface temperature. For single-chip devices
we propose to use an unambiguous definition for the junctionto-
case thermal resistance as a key parameter, based on a transient
measurement technique with much higher repeatability
also for very low thermal resistances compared to a two-point
thermal resistance measurement. The technique is illustrated
on thermal transient measurements of power MOSFETs. A
comparison between different thermal coupling to the ambient
is used to demonstrate the method’s capability to reveal even
subtle internal details of the package. The concept is extended
to multi-chip and stacked-chip structures, where transfer impedances
have to be introduced. Here, the dynamic properties
of the package are important and complex impedance mapping
is the proper way to characterize the package.
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