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74LS195A/54LS195A pdf datashee
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2008-08-06
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54LS195A/DM74LS195A
4-Bit Parallel Access Shift Register
General Description
This 4-bit register features parallel inputs, parallel outputs,
J-K serial inputs, shift/load control input, and a direct overriding
clear. All inputs are buffered to lower the input drive
requirements. The registers have two modes of operation:
Parallel (broadside) load
Shift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits of
data and taking the shift/load control input low. The data is
loaded into the associated flip-flop and appears at the outputs
after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load
control input is high. Serial data for this mode is entered at
the J-K inputs. These inputs permit the first stage to perform
as a J-K, D, or T-type flip-flop as shown in the truth table.
Features
Y Synchronous parallel load
Y Positive-edge-triggered clocking
Y Parallel inputs and outputs from each flip-flop
Y Direct overriding clear
Y J and K inputs to first stage
Y Complementary outputs from last stage
Y For use in high-performance:
accumulators/processors
serial-to-parallel, parallel-to-serial converters
Y Typical clock frequency 39 MHz
Y Typical power dissipation 70 mW
4-Bit Parallel Access Shift Register
General Description
This 4-bit register features parallel inputs, parallel outputs,
J-K serial inputs, shift/load control input, and a direct overriding
clear. All inputs are buffered to lower the input drive
requirements. The registers have two modes of operation:
Parallel (broadside) load
Shift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits of
data and taking the shift/load control input low. The data is
loaded into the associated flip-flop and appears at the outputs
after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load
control input is high. Serial data for this mode is entered at
the J-K inputs. These inputs permit the first stage to perform
as a J-K, D, or T-type flip-flop as shown in the truth table.
Features
Y Synchronous parallel load
Y Positive-edge-triggered clocking
Y Parallel inputs and outputs from each flip-flop
Y Direct overriding clear
Y J and K inputs to first stage
Y Complementary outputs from last stage
Y For use in high-performance:
accumulators/processors
serial-to-parallel, parallel-to-serial converters
Y Typical clock frequency 39 MHz
Y Typical power dissipation 70 mW
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