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DS1746 pdf datasheet (Y2K兼容、非易
消耗积分:3 |
格式:rar |
大小:777 |
2008-08-10
385288
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DESCRIPTION
The DS1746 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
128k x 8 nonvolatile static RAM. User access to all registers within the DS1746 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the date of each month
and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double-buffered system also prevents time
loss as the timekeeping countdown continues unabated by access to time register data. The DS1746 also
contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out of
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low VCC as errant access and update cycles are avoided.
The DS1746 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
128k x 8 nonvolatile static RAM. User access to all registers within the DS1746 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the date of each month
and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double-buffered system also prevents time
loss as the timekeeping countdown continues unabated by access to time register data. The DS1746 also
contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out of
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low VCC as errant access and update cycles are avoided.
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