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IEEE Standard VHDL Language Re
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2008-10-21
李鸿洋
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IEEE Standard VHDL
Language Reference Manual
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 21 March 2002
IEEE-SA Standards Board
Abstract:
VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation
intended for use in all phases of the creation of electronic systems. Because it is both machine readable
and human readable, it supports the development, verification, synthesis, and testing of hardware
designs; the communication of hardware design data; and the maintenance, modification, and
procurement of hardware. Its primary audiences are the implementors of tools supporting the language
and the advanced users of the language.
Keywords:
computer languages, electronic systems, hardware, hardware design, VHDL
Language Reference Manual
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 21 March 2002
IEEE-SA Standards Board
Abstract:
VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation
intended for use in all phases of the creation of electronic systems. Because it is both machine readable
and human readable, it supports the development, verification, synthesis, and testing of hardware
designs; the communication of hardware design data; and the maintenance, modification, and
procurement of hardware. Its primary audiences are the implementors of tools supporting the language
and the advanced users of the language.
Keywords:
computer languages, electronic systems, hardware, hardware design, VHDL
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