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在Xilinx CoolRunner系列的XPLA3 CPL
消耗积分:3 |
格式:rar |
大小:333 |
2009-05-13
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An interface to the 8051 microcontroller has been implemented in a CoolRunner XPLA3 CPLD.
This design consists of a state machine that interprets the 8051 bus cycles to read and write
data to a set of registers called a register file. A high-level block diagram is shown in Figure 1.
Communication between the 8051 microcontroller and the application logic is accomplished
through a register file. The 8051 microcontroller writes data to the register file to configure and
control the application logic. The application logic writes status information and service
requests to the microcontroller through the register file. Data transfer is also done through
registers. Flags can be designed that denote when registers are empty and/or full depending
on the application. The number of registers and their bit definitions are defined in general terms
and should be customized for the application.
This design consists of a state machine that interprets the 8051 bus cycles to read and write
data to a set of registers called a register file. A high-level block diagram is shown in Figure 1.
Communication between the 8051 microcontroller and the application logic is accomplished
through a register file. The 8051 microcontroller writes data to the register file to configure and
control the application logic. The application logic writes status information and service
requests to the microcontroller through the register file. Data transfer is also done through
registers. Flags can be designed that denote when registers are empty and/or full depending
on the application. The number of registers and their bit definitions are defined in general terms
and should be customized for the application.
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