资料下载
×
PLB Block RAM(BRAM)接口控制器
消耗积分:0 |
格式:pdf |
大小:583 KB |
2012-02-10
分享资料个
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
This controller supports the PLB V3.4 byte enable architecture.Any access size up to the width of the PLB data bus ispermitted. The PLB BRAM Interface Controller is the interfacebetween the PLB and the bram_block peripheral. ABRAM memory subsystem consists of the controller alongwith the actual BRAM components that are included in thebram_block peripheral. If the text-based MicroprocessorHardware Specification (MHS) file is used for design entry,then the bram controller and bram_block must both beexplicitly instantiated.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
