资料下载
×
CD4724BC.pdf
消耗积分:2 |
格式:rar |
大小:122 |
2008-04-02
分享资料个
The CD4724BC is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E),
active high clear input (CL), a data input (D) and eight outputs
(Q0–Q7).
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is
LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are
LOW. When clear (CL) is HIGH and enable (E) is LOW, the
channel demultiplexing occurs. The bit that is addressed
has an active output which follows the data input while all
unaddressed bits are held LOW. When operating in the
addressable latch mode (E = CL = LOW), changing more
than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the
memory mode (E = HIGH, CL = LOW).
Features
n Wide supply voltage range: 3.0V to 15V
n High noise immunity: 0.45 VDD (typ.)
n Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
n Serial to parallel capability
n Storage register capability
n Random (addressable) data entry
n Active high demultiplexing capability
n Common active high clear
address inputs (A0–A2), an active low enable input (E),
active high clear input (CL), a data input (D) and eight outputs
(Q0–Q7).
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is
LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are
LOW. When clear (CL) is HIGH and enable (E) is LOW, the
channel demultiplexing occurs. The bit that is addressed
has an active output which follows the data input while all
unaddressed bits are held LOW. When operating in the
addressable latch mode (E = CL = LOW), changing more
than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the
memory mode (E = HIGH, CL = LOW).
Features
n Wide supply voltage range: 3.0V to 15V
n High noise immunity: 0.45 VDD (typ.)
n Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
n Serial to parallel capability
n Storage register capability
n Random (addressable) data entry
n Active high demultiplexing capability
n Common active high clear
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
