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基于流水线重构技术的16x16位乘加器的设计
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2009-06-22
贾桂林
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比较了几种16x16 位乘加器的实现方法，给出了一种嵌入于微处理器的基于流水线
重构技术的16x16 位乘加器的设计方案，该设计可完成16bit 整数或序数的乘法或乘加运算,并提高了运算的速度，减少了面积。利用Cadence EDA 工具对电路进行了仿真，仿真结果验证了设计的准确性。
关键词：乘加器; 乘法器; 流水线
Abstract: This paper compares some methods of 16x16 multiplier accumulator design,
and describes a pipelined and reconstructed technology to achieve 16x16-bit
multiplier accumulator embedded in an MCU(Micro-Control Unit). which supports both
signed and unsigned integer multiplication and multiplication-accumulation, at the
same time ,this method improves operation speed and reduces the area. successfully
simulated in Cadence EDA tools.
Key words: Multiplier accumulator circuit; Multiplier; Pipeline
重构技术的16x16 位乘加器的设计方案，该设计可完成16bit 整数或序数的乘法或乘加运算,并提高了运算的速度，减少了面积。利用Cadence EDA 工具对电路进行了仿真，仿真结果验证了设计的准确性。
关键词：乘加器; 乘法器; 流水线
Abstract: This paper compares some methods of 16x16 multiplier accumulator design,
and describes a pipelined and reconstructed technology to achieve 16x16-bit
multiplier accumulator embedded in an MCU(Micro-Control Unit). which supports both
signed and unsigned integer multiplication and multiplication-accumulation, at the
same time ,this method improves operation speed and reduces the area. successfully
simulated in Cadence EDA tools.
Key words: Multiplier accumulator circuit; Multiplier; Pipeline
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